`timescale 1us/1ps


module tb_key_beep();

reg sys_clk;
reg sys_rst_n;
reg key;

wire beep;

/*iverilog */
initial
begin            
    $dumpfile("wave.vcd");        //生成的vcd文件名称
    $dumpvars(0, tb_key_beep);    //tb模块名称
end
/*iverilog */

initial begin
    sys_clk = 1'b0;
    sys_rst_n = 1'b0;
    key = 1'b1;
    #60 sys_rst_n = 1'b1;
    #40 key = 1'b0;
    #160 key = 1'b1;
    #40 key = 1'b0;
    #100 key = 1'b1;
    #40 key = 1'b0;
    #220 key = 1'b1;
    #40 key = 1'b0;
    #240 key = 1'b1;
    #40
    $stop; //必须要这个，iverilog停止仿真
end

always #10 sys_clk=~sys_clk;

top_key_beep u_top_key_beep(
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n), 
    .key(key),

    .beep(beep)
);

endmodule